ITR: Scalable Molecular Electronics

Carnegie Mellon University, Pittsburgh PA

Investigators

Abstract

PROPOSAL ABSTRACT Scalable Molecular Electronics We are approaching the end of a remarkably successful era in computing: The era where Moore's Law reigns, where processing power per dollar doubles every year. This success is based in large part on advances in complementary metal-oxide semiconductor (CMOS)-based integrated circuits. Although we have come to expect, and plan for, the exponential increase in processing power in our everyday lives, today Moore's Law faces imminent challenges both from the physics of deep-submicron CMOS devices and from the enormous costs of chip masks and next-generation fabrication plants. A promising alternative to CMOS-based computing being investigated is chemically assembled electronic nanotechnology (CAEN). Electronic nanotechnology (EN) constructs electronic circuits out of nanometer-scale devices that take advantage of quantum-mechanical effects. The fundamental strategy of CAEN is to substitute compilation time (which is inexpensive) for manufacturing precision (which is ex-pensive). The research will be directed at integrating defect measurements with computer architecture and compiler technology to create circuits from chemically assembled structures. Using EN to build computer systems requires new ways of thinking about computing devices; spanning everything from circuits to compilers. Unlike conventional CMOS, CAEN cannot be used to construct complex structures. Instead, one fabricates dense regular (but potentially defective) structures, which we call nanoFabrics, that can be programmed after fabrication to implement complex circuits. The proposed research investigates how to scale CAEN to create useful computational devices with more than 10^10 gate-equivalents per cm^2 by developing new circuit technology, reconfigurable computing, defect tolerance, architectural abstractions and innovative compiler technology While the researchers will not be designing the EN devices themselves, their goal is to show how they can be used to create computing devices and guide EN scientists in their development of the underlying technology. The investigators approach this problem at four levels: Logical Building Blocks: The researchers will develop models of EN devices and new circuit simulation technology that will allow predictions of performance across important metrics such as power, speed, density, area, and delay. These models will be used to design and determine the characteristics of logical circuit building blocks, nanoBlocks, for computing systems. Manufacturing: Due to the nature of EN and specifically CAEN fabrication, the devices will have defects. The investigators will develop methods which will allow systems based on EN devices to transparently work in the presence of such defects. Computer Architecture: The researchers will develop a hierarchy of abstract machines that support re-configurable computing and hide complexity. A split-phase abstract machine (SAM) will be used to partition programs into processes, which will be mapped to an abstract machine composed of tiles arranged on a 2-D grid. Each tile will contain four components: a finite state machine, a data path segment, a local memory, and a router. Tiles may be grouped together into a complete pipelined datapath. The tiles themselves will be implemented in nanoBlocks, the basic unit of the nanoFabric. Compilation: Compilation technology will be developed to map programs written in general-purpose programming languages, e.g. C or Java, to nanoFabrics. The research will focus on ensuring that the compiler will scale to nanoFabrics, which can have hundreds of millions of components. The compiler decomposes an application into a series of independent SAMs based on control flow and memory access patterns. They are developing a new intermediate representation with a precise semantics that turns all control flow into data flow. The IR unifies predication, speculation and static-single assignment and makes explicit data flow, control flow, and synchronization. This leads to an enormous simplification of many optimizations and provides the framework for formal translation and optimization validation of the compiler. This research has the potential to utilize, and guide the development of, electronic nanotechnology to inexpensively produce low-power circuits a million times more dense than conventional CMOS circuits.