Reducing Frequency via Speculation and Fall-Back Recovery

North Carolina State University, Raleigh NC

Investigators

Abstract

Mueller, Frank CCR-0208581 " Reducing Frequency via Speculation and Fall-Back Recovery" Conserving power is a key issue in embedded computing. At present, significant power is wasted because embedded system designers lack detailed knowledge of the processing speed needed by applications. Naive worst-case timing analysis exaggerates the required processor frequency, especially as software and hardware complexity increases. This work puts forth a two-tier approach to reduce the processor frequency of complex embedded systems. First, tight worst-case timing analysis reduces the perceived upper bound on the number of cycles consumed by tasks. This reduces the maximum frequency, saving power. Second, architecture simulation and processors with dual frequency/voltage modes enable significant additional power savings. Architecture simulation produces an approximate worst-case timing estimate, which does not have to be safe and, consequently, is the basis for a very low speculative frequency. A higher recovery frequency is utilized as a fall-back mode to ensure safe operation bounded by tight worst-case timing analysis, as delivered in the first approach. These two approaches complement each other. They initially reduce the power requirements by a significant amount when compared with the naive approach. Additionally, they reduce power requirements further by exploiting simulation to accurately