Compiler-driven Design Space Exploration for Multiple FPGA Systems

University Of Southern California, Los Angeles CA

Investigators

Abstract

This project focuses on system-level mapping of applications written in imperative programming languages such as C to multiple FPGA computing systems by the synergistic collaboration of program analysis, parallelizing compiler technology and behavioral synthesis tools. The proposed research addresses system-level partitioning and scheduling of the execution of tasks among computing cores based on high-level program analysis as well as managing the storage and movement of data between both internal and external memories and between tasks. This project is the first comprehensive, and automatic, integration of parallelizing compiler technology with EDA synthesis. It is also the first attempt to integrate in a compiler high-level loop transformations guided by estimates provided by commercially available synthesis tools. The end result is a realistic and accurate design space exploration strategy we believe is widely applicable to current and future multiple FPGA systems as well as future System-On-a-Chip (SoC) systems. An automated application mapping approach that addresses system-level issues as proposed in this research will ultimately allow designers to explore a wider range of application mapping strategies for SoC systems.