SBIR/STTR Phase II: A Low Cost Semiconductor Metallization-Planarization Process

Faraday Technology, Inc, Englewood OH

Investigators

Abstract

This Small Business Innovation Research Phase II Project will establish market demand for a novel electrically mediated leveling technology and position the technology for market launch via a joint venture. The specific Phase II objectives are: 1. Scale-up and demonstration of the electrically mediated process on eight inch wafers, 2. Development of a process library for feature sizes 1-5 down to 0.17 microns, and lower, and 3. Design of a "proof of concept" plating tool. Preliminary concept design of a plating tool incorporating the electrically mediated process will be performed by an outside firm. The sustainable competitive advantage associated with the project for leveling is cost. Minimal overplate will eliminate or minimize the need for chemical/mechanical planarization (CMP) by reducing the copper waste slurry compared to the state-of-the-art copper metallization processes. This in turn would eliminate the associated control, environmental, and cost issues.