CAREER: INVESTIGATING ELECTROSTATIC DISCHARGE PROTECTION IN ULSI ICs DOWN TO NANO-SCALE: SIMULATION, MODELING & EXPERIMENTS

Illinois Institute Of Technology, Chicago IL

Investigators

Abstract

Electrostatic Discharge (ESD) failure is a devastating reliability problem to VDSM (very-deep-sub-micron) and nano-scale Si ULSI IC technologies. It is imperative to investigate ESD failure fundamentals and on-chip ESD protection theories focusing on the following challenges: 3D mixed-mode ESD simulation methodology; accurate high-current ESD modeling; whole-chip ESD design synthesis, advanced ESD protection solutions for ULSI ICs, ESD protection for super-GHz RF ICs, ESD protection for nano-scale as well as wide-bandgap semiconductor IC technologies. The PI proposes a career development plan that addresses these challenges. Proposed research activities consist of six tasks: to investigate advanced on-chip ESD protection phenomena in ULSI ICs by developing a novel 3D mixed-mode ESD simulation methodology; to investigate ESD protection fundamentals by developing accurate high-current ESD device models; to develop a full-chip ESD design verification CAD tool called ESDcat; to explore novel ultra-fast ESD protection solutions for sub-100nm ULSI ICs, to explore ESD protection for future nano-technologies, and to extend ESD research to super-GHz RF ICs and wide-bandgap semiconductor, GaN. Since ESD phenomena are geometry-dependent involving complex electro-thermal-process-device-circuit coupling, the proposed research procedures take full-scale mixed-mode approaches that investigate ESD fundamentals in a fully-coupled process-device-circuit-electronic-thermal closed-loop in 3D format. A 3D parallel ESD model network is proposed for accurate high-current ESD modeling. ESDcat enables chip level ESD synthesis and verification at both schematic and layout levels. Nano-scale ESD research will take into account the ballistic phonon scattering effect. ESD for wide-bandgaps will focus on Si-compatible GaN ICs. End results include insights into ESD mechanisms, CAD tools for further investigation and design of ESD protections for various IC technologies, e.g., CMOS, BiCMOS, SOI, SiGe, GaN, RFIC, and Cu interconnects. Both new ESD theory and immediate industrial applications are expected. The education plan centers on: new curriculum development; integration of microelectronics research and education; student mentoring and community services; and university-industry collaboration. Specifically, activities include: develop five courses/labs in a five-year period; pursue an improved microelectronics teaching approach; establish an Integrated Electronics Laboratory, a Virtual IC Fab facility, and TCAD/ECAD Design Studios; advising students in conducting inter-professional projects; develop a undergraduate industrial co-op program; and involving minority/women students in microelectronics research. This five-year education proposal is integrated into the departmental redevelopment plan in microelectronics