CAREER: Soft Instruction Set Computing

University Of Washington, Seattle WA

Investigators

Abstract

With each successive generation of microprocessors designers push the envelopes of technology and complexity. But these factors are conspiring to make the accepted practice of custom ASICs, and generational processors obsolete. Overhead costs such as design, validation, mask-generation, and test are growing and will make it prohibitive to continue with the current strategies. Concurrent with this trend is the growing realization that we are well past the point of diminishing returns for enhancing single-threaded computational performance. The future will migrate us towards ubiquitous parallel models of execution. Finally, users are starting to demand not just performance but reliability and security from their computing infrastructure. While the obvious substrates are sea-of-gates FPGAs, they are highly inefficient and do not take advantage of the wealth of processor research conducted over the last 50 years. Instead, we propose SISC, or Soft-Instruction-Set-Computing. A SISC processor is a universal processor, with no fixed legacy instruction set architecture, and no fixed interface to the surrounding system envi-ronment. However, it does exploit the best features of both fixed-logic superscalar processors and fine-grained FPGAs to provide an efficient, generic, computing substrate on which to experiment and build the secure, robust and distributed systems of the future. We will demonstrate the capabilities of configurable substrates by showing that SISC processors provide efficient emulation of existing legacy instruction set architectures, a platform to provide peek performance on streaming data-flow applications, a unification of single, multi-threaded and multi-processor architectures, a computing device on which to provide application-specific architecture security, integrated hardware support for high-level languages and a flexible substrate for enhanced undergraduate and graduate level computer architecture research. These application goals will drive our research in the design of a truly universal computing substrate. We expect the following products from this career plan: 1. A configurable processor design capable of emulating most modern instruction sets and a platform on which to construct new secure application architectures. 2. An infrastructure of simulation tools, emulation techniques, and hardware prototypes to demonstrate the benefits of reconfigurable processing substrates. 3. Automated compilation algorithms and tools for runtime customization of the SISC architecture. 4. A set of secure application compilation targets and operating system techniques to dynamically apply them as a response to network attacks. 5. Students trained in efficient system design and rigorous evaluation methodologies through research, student workshops and new courses.