CAREER: Memory Controller Interconnect and Policy Determination

Michigan Technological University, Houghton MI

Investigators

Abstract

The gap between microprocessor and memory system cycle times has been increasing over the past 15 years. In practice, because of the many levels in the memory hierarchy and interconnection busses between the processor and DRAM, a primary memory access may take 200 processor clock cycles from request to response; more than 50% of this latency is due to the memory hierarchy and interconnect. This research will focus upon the reduction of this fraction by novel interconnect techniques and increased focus on the DRAM controller management policies. As the amount of state present in DRAM devices increases, the available set of memory controller policy decisions also increases; this increased flexibility allows an intelligent memory controller to optimize controller policies to achieve increased performance. This research will examine the potential for improved performance when the memory controller changes from a static control policy to a dynamic control scheme. This impact will be simulated over a variety of interconnection topologies from the current NorthBridge to a CMP architecture with multiple DRAM busses.