CAREER: DSP-Enhanced Low-Voltage Signal Processing in Submicron CMOS

Oregon State University, Corvallis OR

Investigators

Abstract

DSP-Enhanced Low-Voltage Signal Processing in Submicron CMOS Today's electronic systems are strongly influenced by the dramatic advancement of submicron complementary metal-oxide-silicon (CMOS) integrated circuits (IC) technology as the size of transistors shrink to extreme dimensions. Because of the shrinking size of transistors, the digital signal processing (DSP) power and efficiency of digital computation grow exponentially; however, the equally decreasing operating voltage of the transistors leads to design problems for mixed analog-digital circuits which are part of all digital processors. By taking advantage of the CMOS down-scaling trend that increases DSP capability, this research combines the developmental efforts in both low-voltage analog circuit techniques and optimum architectures for DSP enhancements. This research systematically explores various architectures, develops and compares adaptive algorithms and digital correction techniques, studies the effects of analog imperfections in deep submicron CMOS, and obtains the fundamental limits of digital compensation and calibration. In this research, two IC design methods are created and expanded to overcome the analog/mixed-signal design challenges of very deep submicron CMOS technologies. The first explores new architectures and techniques capable of maximizing the power of DSP for enhancing analog and mixed-signal circuit performance, including DSP-enabling architectures, use of multi-signal paths and taking advantage of inherent structures for error estimation, and merged system calibration of multi-stage architectures. The second explores new analog circuit design techniques for ultra low-voltage operation that is fully compatible with submicron CMOS, focusing on fast low-voltage switching schemes, analog-error insensitive and DSP-corrected low-voltage structures, and linear low-voltage input sampling circuits.