CAREER: Signal Integrity Fault Modeling and Testing in High-Speed SoCs

University Of Texas At Dallas, Richardson TX

Investigators

Abstract

As we approach 100nm technology, the impact of interconnect on signal integrity is becoming one of the main concerns in testing gigahertz system-on-chips (SoCs). Voltage distortion (noise) and delay violations (skew) contribute to signal integrity loss and ultimately functional error, performance degradation, shorter life and reliability problems. This research investigates a methodology to model and test signal integrity in deep-submicron high-speed interconnects that bind the internal cores in a SoC. The following issues are being explored: a) the development of a unified integrity fault model, independent of technology, that includes various problems occurring on the SoC's high-speed interconnects such as crosstalk, overshoot, skew, etc.; b) the establishment of a test generation technique that finds test patterns to stimulate maximal (worst case) integrity loss on the interconnect network; c) the implementation of noise detector (ND) and skew detector (SD) cells, to detect noise and skew violations (integrity loss) over a period of operation; and d) the design of a cost- and time-efficient readout architecture to transfer the integrity information that ND and SD cells accumulate. As part of educational plan, we are: 1) developing a two course sequence on ASIC/SoC design and test with emphasis on high-frequency issues; 2) involving undergraduate students in general, and minorities in particular, in VLSI/ASIC/SOC test research. 3) advocating for greater CAD tool use in early stage of CE/EE curriculum.