CAREER: Improving Technology-EDA Integration Through Interconnect Design Tools for Nanometer Design

Regents Of The University Of Michigan - Ann Arbor, Ann Arbor MI

Investigators

Abstract

The goal of this research program is to explore tools, models, and design practices that shed light on the relationship between silicon technology and the direction of future EDA tools. The current education, research, and commercial semiconductor and EDA communities are set up in a way that virtually guarantees a knowledge gap between the cutting edge of CMOS technology and state-of-the-art design automation. The best current example of this knowledge gap is on-chip inductance. A large part of this project focuses on developing models, metrics, and design approaches to assess and ameliorate the impact of inductance on circuit performance. This includes a range of RLC-based models varying in accuracy and complexity that target different stages of the design flow ranging from standard cell characterization to late-mode full-chip timing. Other impending knowledge gaps being studied in this research program include: 1) standard cell interconnect libraries to leverage predictability and maintain performance, and 2) scalable global signaling alternatives to CMOS repeaters for nanometer design (feature sizes < 100 nm). The education component of this CAREER program has two broad aims: 1) introduce students to the role of on-chip interconnect on circuit performance early and often, and 2) transfer a diverse population of students to industry with relevant design experience via group design projects.