Compiler-Inserted Control Independence Information for Latency Hiding and Reduced Branch Cost

Louisiana State University, Baton Rouge LA

Investigators

Abstract

Modern processors predict the outcome of branch instructions and speculatively fetch instructions on the predicted path. If the prediction is wrong the speculatively fetched instructions are squashed (deleted) and fetch continues on the correct path. Techniques will be investigated that will reduce the number of such squashed instructions. With compiler and hardware assistance instructions that would normally be squashed and later re-fetched are identified and specially handled so they can be retained. Another approach to be investigated is to delay the fetch of instructions that might have to be squashed, in their place fetching instructions that would be executed regardless of branch outcome. A memory access latency hiding technique will also be investigated. It works by retiring a portion of the dynamic instruction stream (that is delayed by a cache miss) out of order, if necessary. The techniques will help solve two pervasive problems: the limited speed of integer programs due to branch mispredictions and the reduced performance of certain programs due to long memory latency. Branch misprediction penalty is an increasing function of issue width and pipeline depth; as both of these are expected increase the techniques to be developed will have a greater relative impact.