Optimizing Integrated Memory-Hierarchy Designs

Regents Of The University Of Michigan - Ann Arbor, Ann Arbor MI

Investigators

Abstract

The proposed research will investigate architectural approaches to optimize memory-hierarchy performance, focusing on the gap between the lowest level of on-chip cache and the off-chip DRAM. Prior work has shown that the combination of careful scheduling of prefetch requests on dedicated high-band width DRAM channels and careful placement of prefetch data in the cache can make very aggressive prefetching schemes practical. The proposed work builds on this framework in three directions: integration of multiple prefetch-generation sources, development of prefetching based on run-ahead threads, and integration of prefetching and replacement such that predictions of future access patterns can be applied in both domains. In each of the proposed areas, detailed designs will be developed, tested, and iteratively refined via simulation. As solutions in each area firm up, the results will be integrated into a unified model to work out interactions among the mechanisms. The overall objective of the research is to develop and analyze an integrated memory system that delivers maximum efficiency across a range of DRAM-constrained system workloads. The impact of these design techniques will be to increase the efficiency and performance of the high-performance systems used as database, web, and technical computing servers, increasing their responsiveness and capacity.