Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: Advanced CMOS for Mixed-Mode Systems

University Of California-Los Angeles, Los Angeles CA

Investigators

Abstract

0120366 Woo The PIs propose to investigate the design of CMOS devices, circuits, and architectures in the sub-100nm regime with emphasis on high-performance mixed-signal, and RF applications. The thrust of this work will be device/circuit/architecture co-design targeting critical building blocks of mixed-mode systems. The goals are (1) to understand the fundamental device/circuit issues of deeply scaled CMOS, and (2) investigate and develop novel device engineering with novel thin film materials and new circuit architectures that will enable much superior speed, power, and noise performance. Recently, there is much discussion concerning the scaling of MOSFETs into sub-100nm dimensions. Topics such as alternative high-k gate dielectrics, gate leakage, shallow junction formation, source/drain extension engineering, and channel doping engineering are under intensive investigation. Many fundamental device problems such as short channel effects (DIBL and VTH roll-off), off-state leakage current, parasitic capacitance and resistance, and gate tunneling current are currently being examined. It is apparent that sub-50nm transistors can be realized with very high performance limited primarily by parasitics such as series resistance and capacitance. The challenge is mainly how to reduce the off current. This is fundamentally due to the electro-static coupling between the channel region and the source/drain. Although the PIs can reduce the coupling by scaling the junction depth, the ultra-shallow junction implies high series resistance and worse transistor performance. In order to expand the device-design window and to overcome the above-mentioned difficulties, novel device structures and new material systems need to be explored. So far, most of the advance device technology studies have concentrated on digital applications despite the growing interest in RF CMOS and high-speed mixed-mode circuits for communication and multimedia applications. Until now, technology development does not adequately address the issues of concern to analog circuits. Device models are also not sufficient for accurate circuit simulation. In this project, they propose to investigate the design of CMOS devices, circuits, and architectures in the sub-100nm regime with emphasis on high-performance mixed-signal, and RF applications. They propose to study the "analog nonidealities" of short-channel devices, e.g., gate current, nonlinearity, noise, intrinsic gain, variation of output impedance with the drain-source voltage. CMOS on SOI has been suggested as an alternative to bulk CMOS in sub-150nm regime. In the case of digital applications, the key advantage is probably in low-power circuits. For analog circuits, the choice of partially-depleted technology versus fully-depleted technology is still under debate. In the case of RF applications, the small parasitic capacitance of SOI CMOS is particularly attractive. However, many issues related to the floating body need to be clarified. In this project, the PIs will examine the many issues, such as noise, frequency performance, gain, and linearity of SOI MOSFETs for use in high-speed analog circuits. They will also examine novel sub-50nm device structures such as SiGe CMOS, low noise (buried channel) CMOS on SOI, high-performance LBJT as well as DTCMOS. In the case of SiGe, by having the smaller bandgap SiGe source/drain regions, the built-in potential is reduced and can substantially reduce the DIBL and other short channel effects. In addition, the higher mobilities can also improve the source/drain series resistances.