Efficient and Performance Guaranteed Methods for Order Reduction and Analysis of VLSI Interconnect Circuits

University Of Texas At Dallas, Richardson TX

Investigators

Abstract

The advance of high-speed deep-submicron VLSI technology requires chip interconnect and packaging to be modeled by distributed circuits. Such a detailed modeling level eventually results in large scale linear circuits to be analyzed. Thus, the research objective is to develop new circuit order reduction approach to evaluate the circuit performance and characteristics in a reasonable time period and with a guaranteed performance, as required by real design practice. This project focuses on the following tasks: a) Develop new order reduction approaches that provide guaranteed performance; b) Derive correspondingly high efficiency numerical methods; c) Investigate the methods of maintaining preferred characteristics in the reduced order system as well as related implementation issues; d) Investigate wavelet method application in model order reduction and analysis; and e) Contribute to graduate education at UT- Dallas and UNC-Charlotte. The expected research results will provide efficient and performance guaranteed methods for order reduction and analysis of VLSI interconnect circuits, and their corresponding algorithms and software for simulation test. It will also contribute to engineering and science aspects by the expected research results and software, as well as to graduate education.