Interconnect Length Prediction and Length Prediction Driven Placement

Georgia Tech Research Corporation, Atlanta GA

Investigators

Abstract

Complex ULSI designs will be plagued by a myriad of interconnects problems that could require many design iterations to meet timing, power, area, and noise specifications. To cope with this interconnect dilemma, the current transistor-centric VLSI design flow must evolve into an interconnect-centric design flow; however, for this design flow to develop it must accurately predict the impact of interconnects on the performance of logic megacells at the earliest stages of design. This research effort is focused on developing an accurate prediction of the length of each net in a given netlist during logic design. The novel aspect of this work is that a stochastic wire length distribution model, which has been developed in part by the principal investigator, is being used to aid in this prediction. In addition, prediction methodologies that give the designer the ability to choose from a set of possible wiring configurations is emphasized. An integral part of this prediction methodology is the incorporation of the wire length predictions into length prediction driven placement algorithms. The significance of this proposed research is that highly accurate wire length predictions could substantially enhance the accuracy of early timing analysis and give the designer greater flexibility in finding solutions to overcome impending interconnect limits.