ITR/AP: Modeling and Simulation of Sub-micron VLSI

Texas A&M Engineering Experiment Station, College Station TX

Investigators

Abstract

For the next generation Very Large Scale Integration (VLSI) circuits, the signal delay will be dominated by parasitic resistance (R), capacitance (C), and inductance (L) of the interconnect. The ability to extract RCL parasitic quickly and accurately is crucial to the design and verification of large VLSI circuits. This project will develop innovative algorithms and software for fast and accurate extraction of RCL parasitic of VLSI circuits. The main goal of the project is the design of preconditioned iterative methods for solving the linear systems arising in inductance and capacitance extraction problems. Solvers for the inductance problem will use a novel solenoidal basis approach to precondition a reduced system implicitly, leading to rapid convergence of the iterative methods. Fast approximations to the matrix-vector products with dense system matrices will be computed using efficient hierarchical methods. Parallelism in the algorithms will be exploited to develop high-performance software that is capable of tackling large problems. Software developed for this project will be portable across a variety of parallel architectures. It is anticipated that the code will deliver the performance necessary for parasitic RCL extraction of deep sub-micron VLSI circuits of realistic sizes.