ITR/SY: SCMP -- A Single-Chip Parallel Computer

Virginia Polytechnic Institute And State University, Blacksburg VA

Investigators

Abstract

This project will investigate the architecture and design of a single-chip parallel computer system. As technology continues to improve and transistor sizes decrease, the latency of on-chip interconnect wires will have a greater impact on the performance of computer systems. In the future, computer designers will need to develop architectures that avoid the use of long interconnect wires in order to reduce the effect of this latency. One such approach would be to include a number of small, simple processors together on a single chip, forming a single-chip parallel computer. This would reduce the effect of the latency because the length of the interconnect wires would depend on the size and complexity of the individual processors, not the size of the entire system. By keeping the processors simple, long interconnect wires will not be necessary. The challenge to designing such a system is determining the features that the architecture must include. This research project will investigate architectural features that provide low-overhead support for parallel programs, applying them to the design of the SCMP (Single-Chip Message-Passing) parallel computer. Through the extensive use of simulation, the design and performance of the SCMP system will be analyzed and compared to other computer architectures.