Performance Driven Layout and Logic Synthesis

University Of California-Santa Barbara, Santa Barbara CA

Investigators

Abstract

The increased chip complexity causes that average interconnect lengths increase and proportionally larger and larger fraction of chip's area is occupied by interconnects. This proposal addresses several is-sues related to interconnects in submicron technologies. We will concentrate on simultaneous switching cross-talk noise effects in RC interconnects. Our goal here is to develop efficient, easy to compute and accurate bounds on delay in the presence of crosstalk and to characterize and prevent propagating crosstalk signals. Besides correcting the crosstalk caused prob-lems we will also develop methodologies of circuit optimization in the presence of crosstalk. We will develop gate sizing tool, buffer insertion, spacing and net reordering which will consider both cross-talk and delay. At the same time we will explore regularity at the Boolean level to achieve layouts with mostly local interconnects. The ultimate goal is to develop logic synthesis methodology which would produce highly reg-ular layout structures without large area penalty. We propose to continue our work on wave steered design methodology and we will develop tools for logic synthesis and physical design of such circuits.