CAREER: An Integrated Approach to Fault Tolerance in Discrete-Time Dynamic Systems

University Of Illinois At Urbana-Champaign, Urbana IL

Investigators

Abstract

As the complexity of dynamic systems and networks grows through the continuous deployment of embedded systems and the availability of novel sensor and actuator technologies, the likelihood of temporal or permanent failures at certain components or communication links increases significantly and the consequences can become highly unpredictable and severe. Even within a single digital device, the reduction of voltages and capacitances, the shrinking of transistor sizes and the sheer number of gates involved has led to a significant increase in the frequency of so-called "soft-errors," and has prompted leading semiconductor manufactures to admit that they may be facing difficult challenges in future. The occurrence of failures becomes a major concern when the systems involved are life-critical (such as military, transportation or medical systems), or operate in remote or inaccessible environments (where repair may be difficult or even impossible). The synergistically developed research and educational programs of this project aim at obtaining systematic approaches for modeling, detecting, identifying and correcting failures in order to ensure the proper functionality of discrete-time dynamic systems or networks. Unlike traditional control where the goal is to stabilize a given dynamic system (while perhaps maintaining some sort of optimality in the applied control input), a fault-tolerant design aims at ensuring that any deviation from the expected system behavior is confined within a small time interval (usually one discrete-time step). In addition, the designer of a fault-tolerant system needs to account for the possibility of failures in the sensors or communications links, or even in error detecting/correcting mechanism itself. This project takes a system-theoretic viewpoint towards the design of fault-tolerant dynamic systems. The main goals are to obtain resource-efficient fault-tolerant implementations and to characterize their fundamental limitations by jointly exploiting system-, coding-and information-theoretic techniques.