Giga-Scale System-On-A-Chip Design

University Of California-Los Angeles, Los Angeles CA

Investigators

Abstract

This project is to establish an international center for research on giga-scale system-on-a-chip (SOC) designs. It involves researchers from U.S., Taiwan, and China. The center is being supported by the National Science Council (NSC) in Taiwan and the Chinese National Science Foundation (CNSF) to support the activities by researchers from Taiwan and China respectively. Focus of the project is on innovative design methodologies, tools, and algorithms that enable efficient giga-scale SOC integration in nanometer technologies. Research activities include investigation and development of efficient SOC synthesis tools and methodologies, SOC verification, test, and diagnostic technologies, and an SOC design driver that motivates and validates various synthesis, verification, and test techniques developed during the course of this research project. The design driver is a SOC design of a network processor, which includes embedded CPUs, DPSs, FPGAs, and various kinds of memory components. The research on SOC synthesis tools and methodologies includes design specification, design partitioning, synthesis and optimization for embedded DPSs and FPGAs, physical synthesis for full-chip assembly, and synthesis techniques for design re-use. The research on verification and test focuses functional verification, self-test using on-chip programmable logic, analog and mixed-signal self-test, and test for embedded memories.