SGER: Design of MEMS Probe for Testing Nano-Scale Interconnects

Arizona State University, Scottsdale AZ

Investigators

Abstract

The next generation integrated circuit (IC) chips will contain nano-scale high-density interconnects with thousands of I/O pins. Due to the physical size of conventional needle probes, the existing probe method of characterizing and testing chips is no longer a viable technique as the number of I/Os increases. This project proposes to investigate the feasibility of using micro-electro-mechanical systems (MEMS) technology to probe CMOS circuits on wafer level. This project focuses on (1) the development of high frequency electrical models of nano-scale on-chip interconnects and CMOS circuits, (2) the fabrication of a novel MEMS probe structure for testing high-density circuits, and (3) the demonstration of the MEMS probe structure to characterize circuits in nano-scale design.