CAREER: Interconnect Dominant ULSI Designs: A New Paradigm for 21st Century IC Design and Education

Georgia Tech Research Corporation, Atlanta GA

Investigators

Abstract

This proposal addresses the applicability of high-speed communication networks to replace on-chip global and semi-global interconnects. Macrocells with the limited number of gates and wires are connected through the communication network. Limiting the number of gates per macrocell is shown experimentally to reduce the number of metal layers needed for circuit implementation. Additionally a basic research on 3-D interconnect standard cell design for predictability of interconnect related parameters is proposed. This is a combined educational and research effort. The goal is to overcome the limitations imposed by ultra-large scale integrated (ULSI) interconnects. Basic research is being conducted is in: (1) the applicability of high-speed on-chip communication networks to replace dedicated semi-global and global interconnects for use in microprocessor, ASIC, or SoC designs; (2) the incorporation of new 3-D interconnect standard cell design for capacitance and inductance predictability and hence timing, power, and area predictability; and (3) educational tools for grades 5-12 that promote student discovery in the problems and opportunities in present and future microprocessor design.