Behavioral Synthesis for Pseudo-Random Resistant Fault Detection

University Of Massachusetts Amherst, Amherst MA

Investigators

Abstract

Conflicting trends in the requirements for system design and testing are leading to a crisis in existing design-for-test methodologies. The need for design cost reduction motivates design approaches which raise the design abstraction level, including high level core-based paradigms. While the design abstraction level rises, the currently accepted fault model is the single stuck-at model at the gate-level. Behavioral fault models are needed which enable both test and validation of complex systems. In addition, test approaches are needed target high-level fault models and achieve good validation and test coverage. This work examines how to use component-specific testability information to target pseudo-random resistant (PRR) faults. Since only a few pseudo-random resistant faults are typically the source of a disproportionately large fraction of test overhead, targeting these faults is a cost effective DFT approach.