ITR: Data Correlation and its Effects on VLSI Testability

University Of Massachusetts Amherst, Amherst MA

Investigators

Abstract

As design-for-test (DFT) research becomes mature, a deep understanding of the relationship among structural features and their mutual effects on testability is needed. Sequential loops are widely accepted as a significant testability problem that must be addressed by the DFT process. Reconvergent fanout is also known to be a problematic structure for testability, however its impact on test has not been thoroughly studied. This project will investigate the relationship between reconvergent fanout, sequential loop length, and aspects of testability including fault coverage, test application time, and test generation time. This understanding will enable the creation of new DFT approaches, which improve testability in a unified way, considering all structural features and their interactions.