ITR: Static and Dynamic Techniques for Latency Hiding in Data-Intensive Applications

Carnegie Mellon University, Pittsburgh PA

Investigators

Abstract

Many of today's performance-critical applications involve manipulating data sets that are either too large or too rarely used to be reliably found in local memory caches or local cache servers. Due to the enormous disparity between processor cycle times and disk and network access latencies, these applications waste a large fraction of their time waiting for data; as we look to the future, this problem is expected to become even worse. To overcome this problem, this research will combine aggressive storage prefetching with intelligent cache management to fully hide the data access latency while using memory resources intelligently. Program transformation tools and runtime support systems will be developed that collaborate to customize memory hierarchy and distributed cache resource management for data-intensive applications. With application-specific guidance of memory, network and disk resources, it is possible to decrease execution times by orders of magnitude. The ultimate goal of the research is for programs to never waste time waiting for data, and for programmers to never waste their valuable programming time thinking about this performance problem.