Si-Based Tunnel Diode Integration with CMOS and SiGe HBTs

University Of Delaware, Newark DE

Investigators

Abstract

The goal of this project is to integrate Si-based tunnel diodes with CMOS and SiGe HBT technology to demonstrate circuits which exhibit higher circuit speed, reduced component count, and lowered power consumption, and which extend CMOS on the Semiconductor Industry Association (SIA) Roadmap without a linewidth reduction. The proposed project would establish an integrated program by involving universities (Delaware and Rochester Institute of Technology) and government research laboratories (Naval Research Laboratory) with the goal of making the first Si-based tunnel diode integrated circuit. The research will focus on simple tunnel diode circuits which combine Si-based tunnel diodes with CMOS and SiGe HBT technology. The work will be synergistic with another project (NSF-ITR) involving Michigan, Delaware, NRL and RIT which proposes to study the new circuits enabled by this technology. This proposed project focuses upon developing integration recipes with CMOS and HBTs. This body of work includes: studying the back-end thermal budget for unmetalized CMOS to withstand tunnel diode processing; finding appropriate cleaning etchants which prepare the surface for MBE overgrowth while being benign to the pre-existing CMOS; develop selective etchants to remove unwanted poly-crystalline MBE growth atop the CMOS; perform MBE overgrowth into pre-defined windows atop source/drain implants; examine possible emitter/base junction displacement with tunnel diode overgrowth; develop selective etchants to mesa etch the TD atop the HBT structure; and realize some simple tunnel diode transistor circuits. The Si-based tunnel diodes have already been developed (NSF CAREER- Berger, DARPA- Ultra Electronics) and are currently being optimized (NSF GOALI-Berger, NRL and Raytheon). SiGe HBT integration will be performed by Delaware and by the NRL team, who have considerable experience in the growth and fabrication of SiGe HBTs. For this proposed project, Dr. Phillip Thompson at NRL will perform the MBE growths, Delaware will perform tunnel diode and SiGe HBT fabrication and testing, and RIT will perform the CMOS fabrication. Strong interaction between the University of Delaware, the Naval Research Laboratory and Rochester Institute of Technology will foster open discussion and dialogue. This proposal seeks to bring together circuit designers, semiconductor device engineers and CMOS technologists for the sole purpose of realizing tunnel diode/transistor circuits on a Si platform. Undergraduate research and student training will play a significant role at Delaware through existing and anticipated NSF REU supplements and at RIT through their student-run CMOS factory and RIT's senior thesis projects. RIT's budget includes an undergraduate researcher. The cross-disciplinary work and site visits to NRL research labs will enhance the educational process.