Productivity-driven Floorplanning

Colorado School Of Mines, Golden CO

Investigators

Abstract

This project studies the floorplanning problem from the standpoint of improving design productivity. The design productivity crisis faced by the semiconductor industry has been well documented in the National Technology Roadmap for Semiconductors, 1997 Edition. Floorplanning has a significant impact on productivity because of its interaction with architectural synthesis during the earlier stages of the design process and with logic and layout synthesis in the later stages of the design process. The research problems that are being addressed by this project include the white space distribution problem, incremental floorplanning, and intelligent post-floorplan analysis. This research is being carried out in consultation with Dr. Naveed Sherwani, Strategic CAD Labs, Intel Corporation.