Modeling Run-Time Reconfiguration

Louisiana State University, Baton Rouge LA

Investigators

Abstract

Run-time reconfiguration (RTR) is a method of computing in which the hardware, usually field-programmable gate arrays (FPGAs), changes structure from one phase to the next of a computation. It has applications in image processing, signal processing, encryption, networking, and other areas. The research develops the necessary foundations to open up RTR to wider usage. The research addresses directions: (1) Development of a layered model of FPGAs suitable for broad exploration of RTR solution approaches, and porting of reconfiguration techniques developed by the investigators and others in the study of reconfigurable meshes to the RTR arena. (2) Design of fault tolerant RTR solutions in both an algorithm-specific context and in a general computational context. (3) Development of ``hardware operating system'' support for users to distance themselves from FPGA details. The research leads to benefits of less hardware, because of reuse of reconfigurable hardware, and faster computation, because of specialization to input. It develops a fundamental understanding of RTR, its power and limitations, and to establish a framework for using it efficiently.