VLSI Arithmetic Logic Schemes and Low-Power High-Performance Circuits for Parallel and Reconfigurable Computations

Suny College At Geneseo, Geneseo NY

Investigators

Abstract

Proposal: CCR 0073469 Title: New VLSI Arithmetic Logic Schemes and Low-Power High-Performance Circuits For Parallel and Reconfigurable Computations PI: Rong Lin ABSTRACT This research investigates several basic parallel and reconfigurable arithmetic and elementary functional unit designs, architectures and algorithms. Recently developed non-binary VLSI shift switch logic schemes and low-power high-performance circuits are used for the study. A set of application specific processors, using the novel logic and the building-block circuits, has demonstrated superiority in VLSI design, which includes high-speed large-size array multipliers, reconfigurable inner product processors and reconfigurable matrix multipliers. Development of a dynamically reconfigurable platform for all of these computations is a major target of this project. The new logic schemes primarily employ shift switch parallel counter units as logic operators, and 4-bit digital signals, representing values ranging from 0 to 3, as logic operands, where only 2-out-of-4 signal bits are subject to value-change at any logic stage in the worst case. This is used to simplify the circuit designs and to reduce the power-dissipation. The main focus of this research is to further explore the properties and advantages of the logic schemes and circuits, and to develop superior applications for parallel and reconfigurable computations. A significant impact on the next generation of microprocessors and SOC designs is expected.