Using Predictor Paradigms to Enhance Memory Hierarchy Performance

University Of Washington, Seattle WA

Investigators

Abstract

The focus of this research is the design and evaluation of hardware assists and software profiling techniques that allow better utilization and performance of the memory hierarchy of high-performance systems. The overall goal is to lessen the impact of the increasing speed discrepency between processors and the various levels of the memory hierarchy. The research methodology will compare the results of offline, optimal algorithms with algorithms that can be feasibly implemented in a memory system, to guage the performance increase possible from prediction triggering, indexing, prediction mechanisms, and feedback. This methodology will be applied to three specific problems: Dynamic line size choice, replacement algorithms for caches with large associativities, and prefetching in lower levels of the memory hierarchy.