Adaptive Systems-on-a-Chip for Low-Power Signal Processing

University Of Massachusetts Amherst, Amherst MA

Investigators

Abstract

Future signal processing systems will use a heterogeneous System-on-a-Chip architecture for performance, flexibility, cost and power efficiency. Components will include programmable DSP and RISC cores, memories, dedicated hardware blocks and embedded field programmable logic cores for flexible and late-bound functionality. Adaptation of the system will be required to track time-varying aspects of the environment. Dynamic reconfigurability can be used to adapt algorithms and architectures to time-varying computations in signal processing applications, thus dramatically reducing average power consumption. The objective of this project is to develop theory, methodology, tools, and demonstration of several adaptive signal processing systems using parameterized macros which can be dynamically configured to adapt to the computation and save power. Improvements to embedded field programmable architectures and circuits will be developed to make them better suited for low-power signal processing applications. This includes hardware and software mechanisms at the chip and system level to support the dynamic reconfiguration of parameterized macros to save power. CAD techniques will leverage recent work in incremental place-and-route, macro-based floorplanning, and statically scheduled communication. New design methods and tools will be evaluated in four realistic and complex DSP systems which all have time-varying computations and tight power budgets: 1) an MPEG2 encoder, 2) an FFT-based wireless receiver, 3) a radar for unmanned aircraft, and 4) a wireless LAN prototype. Collaboration with ENST/Paris is anticipated.