POWRE: Nano-gate Engineering for Ultra-fast CMOS devices

North Carolina State University, Raleigh NC

Investigators

Abstract

0074800 Misra To obtain maximum performance from nanoscale CMOS devices, conventional polycrystalline silicon gate electrodes will have to be replaced by metallic layers. However, any replacement candidate for polysilicon must adhere to several criteria. Firstly, electrodes should not react with the underlying sub-1.0 nm gate dielectric. Secondly, the electrodes must be able to withstand high temperature processing in order to preserve the self-aligned structure of the MOS device, which has been the foundation of today's advanced technologies. Finally, to obtain desired threshold voltage for giga-scale performance, the electrodes must provide specific workfunctions, i.e. NMOS devices will require gates with workfunctions near 4 eV and PMOS devices will require gates with workfunctions near 5 eV. The need for two separate metals significantly complicates the process technology, both in material and cost issues. The goal of this POWRE project is to investigate alternate approaches for nano-gate electrode formation using workfunction modulation of conducting metal oxides. Transparent conducting oxides offer the flexibility of workfunction modulation via chemical composition changes. This property can be used to benefit nanoscale CMOS. The main theme behind this proposed activity is to deposit a single conducting oxide layer on both the NMOS and PMOS region dielectrics and then via non-critical masking steps, selectively implanting certain elements to modulate the workfunction on N and P regions. This would eliminate the need for two separate metal deposition steps and drastically simplify integration issues. Moreover, conducting metal oxides, never before considered for Si gate electrode applications, can also provide superior thermal and chemical stability. If the above proposed activities are feasible, i.e. workfunction of conducting metal oxides can be tuned in to match the CMOS requirements, then this work offers tremendous potential for nanoscale CMOS advancement. ***