Research on Interconnect-Dominated Floorplanning

University Of California-San Diego, La Jolla CA

Investigators

Abstract

The project researches interconnect-dominated floorplanning. The floorplanning organizes the topology of wires and the assignment of buffers while placement and routing are structured as supporting tools to fulfill the design requirements. The project includes exploration of the following. Technology Floorplanning: Given a circuit design project, the technology floorplanning identifies the technology that provides the best interconnect capability in terms of cost and performance. Logic Floorplanning with a Hierarchical Design Framework: A logic floorplanning takes advantage of the design hierarchy and derives the effect of interconnect delay. Physical Layout Floorplanning: Physical layout floorplanning serves as a foundation to support the interconnect optimization operations.