Power Analysis and Optimization Methodologies for Wireless Embedded Nanochips

University Of California-San Diego, La Jolla CA

Investigators

Abstract

This research develops advanced methodologies and tools to enable the design of low-energy embedded system-on-nanochips for future wireless appliances. A system-level power analysis technique is developed which considers the effects of wireless protocols, architectural choices, and nanometer technologies on the energy consumption of the hardware, software, and RF components of a wireless embedded nanochip. Since adaptive on-chip communication is fundamental to such heterogeneous component-based nanochips, analysis and optimization techniques are developed for low-energy on-chip communication architectures and protocols. Static and adaptive analysis and management techniques are developed to extend the battery life of the mobile systems. The techniques are being applied to the design of an adaptive single-chip radio that is being developed to enable wireless multimedia communications.