Kinetics of Ultra-Thin Metal Oxide and Silicate Film Deposition on Silicon

North Carolina State University, Raleigh NC

Investigators

Abstract

Abstract - Parsons - 0072784 Continued scaling of metal/oxide/semiconductor transistors to sub-100 nm gate lengths will require new metal oxide gate insulators with higher dielectric constants to maintain large capacitances (i.e., equivalent to <1nm of SiO2) and minimize gate tunneling currents. Typical low temperature chemical vapor deposition (CVD) processes for metal oxides on silicon result in an unwanted thin (1 to 2 nm) SiO2 or metal silicate layer at the Si/metal oxide interface. The interface structure is determined by the kinetics of individual deposition reaction steps that favor consumption of the silicon substrate, even when the deposited bulk oxide is thermodynamically stable on silicon which indicates a problem for non-native metal oxide/silicon interfaces not encountered in the native SiO2/Si system. Specifically, how does one control the first few angstroms of non-native dielectric deposition on silicon to achieve the required bond structure, composition, and electronic quality at the interface? This problem extends to other heterojunction applications, such as optical interconnects, magnetoresistive devices, bio-functional systems, etc., where atomic-scale control of interface structure is important for device performance. In this project the kinetics of interface layer formation during deposition of yttrium oxide, yttrium silicate, and other metal oxides on silicon will be studied. This will include studies of surface treatment on substrate consumption and interface oxide formation, and electrical performance of silicon/yttrium oxide and silicon/yttrium silicate interfaces. The work will involve direct measurement of deposition reaction kinetics in plasma and thermal CVD, using in-situ infrared spectroscopy and on-line Auger electron spectroscopy. The project will be done in collaboration with Roy Gordon at Harvard University, who will provide various reactants, to determine the effect of metal-organic precursor structure on interface reactions. Atomic layer deposition methods will be used to demonstrate controlled interface abruptness and improved electronic performance. These experiments will help establish new links between surface reactions, process temperature, and electrical performance of deposited thin film dielectrics, and will have implications for controlling interface structures in other sub-nm electronic, optical, and magnetic devices.