SBIR Phase II: Very Large Scale Integrated (VLSI) Implementations of Neuromorphic Virtual Sensors for Intelligent Diagnostics and Control

Mosaix, Llc, Monrovia CA

Investigators

Abstract

This Small Business Innovation Research Phase II project will develop a novel, compact, low-cost adaptive neuroprocessor chip for advanced diagnostics and control in the next generation of low emission "environmentally friendly" vehicles. This digital CMOS VLSI electronic neural network device combines on-chip integration of a fully reconfigurable feed-forward/time-lagged recurrent neuroprocessor module with backpropagation-through-time (BPTT) weight training module. Specifically, the technical objectives are to develop a neuroprocessor chip suitable for direct insertion into an automobile's electronic engine computer (EEC). This stand-alone electronic neural network will function as a co-processor to the EEC's central processing unit (CPU), off-loading it of computationally intensive neural based tasks and enabling event rate automotive diagnostics and control. The neuroprocesor is programmable, allowing it to execute multiple neural network applications on-the-fly; is capable of event rate computational throughput (<<50 microseconds) per appli-cation; is a system-on-a-chip (SOAC) design (stand-alone neuroprocessor with on-chip weight training); and cost effective (<$5/chip). On-chip adaptation will not only enable adaptive control, but will address the problem of fixed weight networks - namely that of enabling on-board self-calibration of electronic and mechanical systems for optimal performance. Applications areas of the proposed neural network formalism cover the following industry sectors: (1) ad-vanced diagnostic and control strategies for low emision vehicles & hybrid electric vehicles in the automotive industry; (2) prognostics and diagnostics of jet engines for the aerospace industry; (3) and adaptive equaliza-tion of cell phones for superior noise rejection in the communication industry.