CAREER: Architecture Issues in DRAM Devices and Systems

University Of Maryland, College Park, College Park MD

Investigators

Abstract

The gap between the processor and memory speeds is a major bottleneck in today's computer systems. Increasing DRAM bandwidth and reducing access time are keys to solving the memory latency problem. There is a relative dearth of architecture studies on DRAM devices and systems; there are therefore many fundamental questions representing open research in the field. This project investigates into the effects of various techniques in designing a DRAM system. Examples include supporting concurrent accesses and determining the extent to which modern CPUs can exploit such support; the effect of multiple channels and whether they be ganged together to increase bandwidth or should they operate independently; and the effect of banking and its optimal degree for DSP and embedded applications. For burst-mode DRAMs, the optimal burst size to accommodate both concurrency and fast end-to-end latency is analyzed in this project. The tradeoffs between the degrees of banking and interleaving, and between bus width and bus speed in power, performance, and cost are also analyzed. The educational plan involves developing a course on memory-systems design and optimization.