Career: Interconnect Planning and Synthesis of Physical Layout for Deep Submicron VLSI Design

Purdue Research Foundation, West Lafayette IN

Investigators

Abstract

With the continued scaling of VLSI technologies, interconnects play a dominant role in determining system performance, power, reliability, and cost. To ensure timing closure of designs, impacts of interconnects must be considered at every design stage. This research is directed at developing an interconnect-centric design methodology that emphasizes interconnect planning and synthesis during physical design flow. Research activities being carried out under this grant include: (a) Developing routability-driven repeater planning algorithms for the optimization of multiple global nets during floorplanning and placement; (b) Developing novel layout synthesis techniques -- topology construction, wire-sizing/splitting and spacing, and repeater insertion -- for the optimization of interconnect delay and signal integrity of on-chip RLC interconnects; (c) Developing global routing algorithms that perform simultaneously the routing of multiple nets and the synthesis of dedicated current return paths; (d) Developing reliable clock synthesis techniques that minimize the risk of current induced noise associated with the switching activities of circuits.